The present invention relates to the growth of hemispherical grained silicon for creating a texturized polycrystalline silicon layer, and more particularly to the use of seed layers from which silicon grains are grown for integrated circuit application.
Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit area.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. An interlayer dielectric material is deposited between the deposition of two conductive layers, which form the capacitor plates. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. Some include the use of new high dielectric materials between the plates. Other techniques concentrate on increasing the effective surface area of the plates by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive plates and interlayer dielectric conform.
One commonly used method of increasing cell capacitance involves further increasing the surface area of the capacitor plates by providing a roughened or texturized plate surface. Roughened polycrystalline silicon (polysilicon, or simply poly) in the form of hemispherical grained silicon (HSG silicon, or HSG polysilicon), for example, has been utilized for the bottom plate of the capacitor. This further increases the effective area of the bottom plate, thus increasing the capacitance of the storage node.
FIG. 1 illustrates the result of a prior art HSG polysilicon forming process in connection with a DRAM cell 10. A pair of word lines 12 are shown isolated by a plurality of vertical dielectric spacers 13, word line insulating caps 14 and an insulating layer 15. A contact window 16 is opened through the insulating layer 15 to expose an active area 17 between the word lines 12. The word lines 12 each overlie either a relatively thick field oxide 18 or a much thinner gate oxide 19. A poly or amorphous silicon layer 20 is then deposited over the insulating layer 15 and through the window 16, contacting the active area 17. In order to provide reasonable conductivity, the silicon layer 20 is lightly doped with n-type dopants.
An extremely thin layer of native oxide 24 is allowed to grow over the silicon layer 20, serving as the seed layer for the HSG polysilicon growth to follow. HSG polysilicon may then be deposited by low pressure chemical vapor deposition (LPCVD), among other techniques, and silicon grains 26 grow about nucleation sites provided by the native oxide 24. A layer of HSG polysilicon 30, which forms the bottom plate of the storage node, results over the native oxide 24. Although not shown in FIG. 1, subsequent process steps include doping the HSG polysilicon 30, depositing a conformal dielectric layer over the bottom plate HSG polysilicon 30, and depositing a conformal polysilicon layer to form the top plate of the storage node.
Subsequent heat cycles and other mechanisms must be implemented to break up the native oxide 24 so that a conductive path is formed between the HSG silicon 30 and poly 20 and the underlying active area 17. Even after break-up, oxide (SiO.sub.2) 24 remains and contributes to the sheet resistance of the bottom plate, lowering capacitance of the memory cell. Moreover, the heat cycles required to break up the native oxide 24 exacerbate unwanted dopant diffusion.
Furthermore, the HSG silicon 30 should be heavily doped to decrease the charge depletion width in the bottom plate, thus increasing capacitance. However, heavily doping the HSG silicon 30 also allows diffusion of the dopants through the silicon layer 20 to the underlying active area 17. For example, phosphorus from solid source P.sub.2 O.sub.5, a commonly employed dopant, diffuses easily through silicon during high temperature anneal steps. The diffused dopants interfere with junction operation and cause current leakage, which reduces charge storage of the memory cell. Although implanted dopants such as arsenic ions diffuse less easily, they are not conformally deposited, they are more expensive, and they do not eliminate diffusion. Reverse diffusion, or "out diffusion" from the active area may similarly occur, changing the dopant profile of the active area and the transistor characteristics.
To provide structural support and adequately low sheet resistance, the silicon layer 20 should be relatively thick (on the order of 500 .ANG.). However, this thick silicon layer 20 occupies a substantial volume of the memory cell, which may otherwise have been available for three dimensional cell structures capable of increasing plate surface area.
Alternative methods of HSG silicon formation are also known, such as those disclosed in U.S. Pat. Nos. 5,320,880, issued to Sandhu et al.; U.S. Pat. No. 5,202,278, issued to Mathews et al.; and U.S. Pat. No. 5,112,773, issued to Tuttle. Since HSG polysilicon formed by these methods must be doped and the underlying silicon allows excessive diffusion, these alternative methods entail similar problems with the diffusion of dopants.